Week #8: Lab Practical Exam: Mid-Semester

Locked
rjagodowski
Posts: 2370
Joined: Fri Sep 04, 2015 6:59 pm

Week #8: Lab Practical Exam: Mid-Semester

Post by rjagodowski »

This week you will individually perform a lab practical exam. You will be required to build a combinational digital logic circuit, construct and complete the truth table for the circuit, and label your schematic with the chip & pin numbers used. You will be given approximately 20 minutes to complete the exercise, and then you will begin the regularly scheduled lab for the week.

A SAMPLE of the actual exercise used in a previous year is attached below. Feel free to review this exercise before you take the lab practical.
EET-210L SAMPLE Lab Evaluation #1 v18.1.pdf
(62.31 KiB) Downloaded 163 times
avkaptyug0001
Posts: 43
Joined: Fri Sep 07, 2018 10:15 am

Re: Week #8: Lab Practical Exam: Mid-Semester

Post by avkaptyug0001 »

Artur completed that lab
kjbusiere0001
Posts: 53
Joined: Fri Jan 26, 2018 10:10 am

Re: Week #8: Lab Practical Exam: Mid-Semester

Post by kjbusiere0001 »

I have completed the lab practical.
Locked

Return to “EET-210 Lab”