Week #9: (11/2-6) Transistor Biasing, AC Transistor Models

Post Reply
rjagodowski
Posts: 1674
Joined: Fri Sep 04, 2015 6:59 pm

Week #9: (11/2-6) Transistor Biasing, AC Transistor Models

Post by rjagodowski »

This week we continue the discussion on Transistor Biasing (DC) and begin the discussion of Transistor Amplifier Operation (AC).

A key point to keep in mind during our discussions: The current gain parameter, beta (also known as hFE), generally has a wide range of values within a specific part number. For example the 2N2222 transistor may have a beta range between 50 to 300. One goal of the various biasing circuits we are discussing is to stabilized the bias point, known as the Q-point, with respect to variations in beta.

We're going to revisit This Link and scroll down to the graph on "Operating Regions" showing the load line & Q-Point. We will again discuss the Q-Point (VCEQ & ICQ) values and why it's important to know those BEFORE we proceed with any A.C. Analysis. We'll also look at the Saturation and Cut-Off points of the load line.

We will begin analyzing a Common Emitter Voltage Divider Biased NPN transistor amplifier for A.C. operation. The example we will work through is the one presented in our Week #8 lab experiment. Check out this link for information about the r-parameter Transistor Model.

We will also discuss some of the parameters for the 2N2222A & 2N3904 transistor spec sheets, specifically those dealing with beta (hFE on the sheet). Here are the pdfs for these two transistors:
2N2222A-Datasheet.PDF
(119.67 KiB) Downloaded 29 times
2N3904_Datasheet.pdf
(188.88 KiB) Downloaded 33 times

Here are some White Board ScreenShots from the 2018 Lecture. The important things to remember while doing the Analysis of these circuit is:
1.) The DC Bias voltages & Q-point must be calculated first, to make sure the transistor is operating in the proper region.
2.) Check that Beta*RE is much larger than R2 of the voltage divider base bias circuit, to minimize loading.
3.) For A.C. Analysis: Assume all Capacitors look like A.C. "shorts" and D.C. "opens".
4.) Choose an A.C. Model for the transistor. We're using a simplified r-parameter model as shown in pics.
5.) Notice for AC Analysis:
  • a.) R1 & R2 are in parallel for the A.C. signal.
    b.) Putting an RL in the circuit effective is in parallel with RC for the A.C. signal.
    c.) An Emitter-Bypass Capacitor is often present to increase the A.C. signal gain.
    d.) Input impedance is the resistance "seen" looking into the transistor circuit.
    • a.) It relates how much this transistor stage "loads down" the previous circuit.
      b.) It can be defined as either the resistance of the entire transistor circuit (including R1 & R2) (usually what is wanted)
      c.) or just the resistance seen looking into the Base (neglecting R1 & R2).
    d.) Voltage Gain is defined as the ratio of the Output Voltage/Input Voltage. Notice the Voltage Gain expressions are fairly complex (unlike the op-amp circuits we're discussing) and we often try to simplify them with approximations.
I'd recommend that you recopy my board notes in your own hand-writing and work through all of the calculations on your own.
EET-200_BJT_CE_ClassA_2018-1030_01.JPG
EET-200_BJT_CE_ClassA_2018-1030_01.JPG (1.77 MiB) Viewed 216 times
EET-200_BJT_CE_ClassA_2018-1030-02.JPG
EET-200_BJT_CE_ClassA_2018-1030-02.JPG (1.65 MiB) Viewed 216 times
EET-200_BJT_CE_ClassA_ACModel_2018-1101-01.JPG
EET-200_BJT_CE_ClassA_ACModel_2018-1101-01.JPG (1.88 MiB) Viewed 216 times
EET-200_BJT_CE_InputImpedance_2018-1101-02.JPG
EET-200_BJT_CE_InputImpedance_2018-1101-02.JPG (1.55 MiB) Viewed 216 times
Post Reply

Return to “EET-200 Lecture”