Week #7: (10/19-21) Adders, Synch. Circuits, PLDs.

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rjagodowski
Posts: 1561
Joined: Fri Sep 04, 2015 6:59 pm

Week #7: (10/19-21) Adders, Synch. Circuits, PLDs.

Post by rjagodowski » Wed Oct 21, 2015 7:41 am

This week we will investigate some simulation circuits for adders, Counters & PLDs (Programmable Logic Devices). Since the actual construction of these devices is rather tedious, we will make use of some Java-enable web applets to demonstrate the principles. (NOTE: Java applets are sensitive to the web-browser and system OS. I seem to have the best luck using Internet Explorer. You can try other browsers/OS's, but if you get errors, use IE instead. If you're concerned about Java insecurities, I can tell you I have not had a problem on this site. But if you're still concerned use the computers in our lab.)

For each link below, read the description for each circuit and then verify it's operation. You do not necessarily need to understand all of the details about how each circuit performs it's task, but you should understand how to use each circuit.

For the PLA in the last link, construct the truth table that will show the outputs Y0 and Y4 as a function of A3A2A1A0. Make sure you understand how this PLA works and how this truth table is implemented.

Assignment: Write a brief description of each circuit & it's operation (a short paragraph or so) for future reference. Note that these circuit files can be edited. In some cases, you might find it helpful to either slow down or speed up a clock signal to better appreciate the operation of a circuit. Right-clicking on a component and then selecting edit object will open a window with the parameters which may be changed. You can zoom out by typing the "z" key; zoom in by typing the "Z" key, and zoom to fit the entire circuit on the screen by typing the "f" key.

JK Flip-Flop Simulation.

Arithmetic Operations:

Half-Adder/Full-Adder.

4-bit Binary Adder/Subtractor using 2's Complement Arithmetic Observe how the Cout bit is the same as the sign-bit for 2's complement arithmetic. Does this circuit have any way of detecting an Overflow or Underflow condition.

Ripple-Carry Adder.

BCD Adder.

Integer Multiplier.

Counters:

Asynchronous Counter. Check out both the UP and DOWN counter, and note the asynchronous CLEAR inputs on each FF. These can be use to put the Counter into a preferred state BEFORE the count begins.

Synchronous UP/DOWN Counter. Notice this counter is synchronous (all FFs are clocked by the same signal), can count UP or DOWN, has an ENABLE and has an ASYNCHRONOUS CLEAR input.

7490, 7492, 7493 Common TTL Counter chips, three different circuits/applications.

Digital Clock #1 and Digital Clock #2.

Programmable Logic Devices:

PLAs

ljbaker0001
Posts: 63
Joined: Fri Sep 11, 2015 10:15 am

Re: Week #7: (10/19-21) Adders, Synch. Circuits, PLDs.

Post by ljbaker0001 » Wed Dec 16, 2015 7:11 pm

completed

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