Week #6: Latches & Flip-Flops

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rjagodowski
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Joined: Fri Sep 04, 2015 6:59 pm

Week #6: Latches & Flip-Flops

Post by rjagodowski »

We'll spend most of today's lecture going over these sheets on NOR and NAND Latches:
Lab 5 RS Latch NOR & NAND Worksheet v20.1.pdf
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This week we will begin the discussion of latches and flip-flops.
Sequential Logic. Latches & Flip-Flops. The content is pretty good BUT skip over it past the title "Sequential Logic SR Flip-Flops". The truth tables are incorrect and will definitely add to the confusion.

REMEMBER: The operation of "SET" causes the Q output to be "1". The operation of "RESET" causes the Q output to be "0". The operation of "HOLD" means that the Q output DID NOT CHANGE. Anytime an input creates a condition where Q = Q', this is an INVALID condition, but a variable cannot be equal to it's complement.

This might be a better tutorial, as it doesn't contain errors in the truth tables that the above link has: SR Flip-Flops from LearnAbout-Electronics.org.

There are some good oscilloscope pics of bouncing switches on this website.

Topics: Discussion on RS Latches from NOR and NAND Gates.
RS Latch applications, D and J-K Flip-Flops. D Flip-Flops, JK Flip-Flops and Counters.
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