NOTE: Next week in lab you will be performing a lab practical exercise on the Digital part of this course. Click here for more details.
This week we will continue discussing Latches, Flip-Flops, Counters, Registers, Adders and Programmable Logic Devices.
Last week I mentioned that latched can be used to debounce a switch. Here's a tutorial on that. Switch Bounce and looked at an example of how an active LOW RS latch can be used to "de-bounce" a switch, as shown in this Sequential Logic Tutorial (scroll down near the end of the page).
This tutorial shows the ladder diagram implementation of an active HIGH RS Latch.
These two YouTube Videos show some good examples & make some good points about switch debouncing, including oscilloscope traces showing the result of the bouncing switch (around the 11 minute point on the first video).
SPDT Debouncing Circuit (Note: This is a good video, but he reverses the Q and Q' latch outputs in his truth table. Watch for it.)
SPST Debouncing Circuit This video introduces Schmidt Trigger devices, which use hysteresis to develop clean, sharp output transitions and can be used to eliminate the effects of switch bouncing as well. The end of this video also mentions that software routines can also be used to debounce a switch input on microcontrollers. We'll discuss that in the EET-260 Microcontroller Applications course next semester.
We'll then discuss Flip-Flops with special emphasis on
Edge Triggered Flip-Flops and the JK Flip Flops and these simulations: JK Flip-Flops & D Flip-Flops. Notice that these are "edge-triggered" flip-flops, which means that the output will only respond to the inputs on the active edge of the clock signal. This is the way most synchronous devices work. The synchronous devices can be designed to either trigger on the "rising edge" of the clock pulse, or the "falling edge" of the clock pulse. When analyzing synchronous circuits it's important to understand this concept.
Edge Triggered Flip-Flops
The next topics will be Combinational Logic Functions.
We will wrap up our discussion of digital logic devices by looking at some simulation circuits for adders, Counters & PLDs (Programmable Logic Devices). Since the actual construction of these devices are rather tedious, we will make use of some Java-enable web applets to demonstrate the principles. (NOTE: Java applets are sometimes sensitive to the web-browser and system OS. I seem to have the best luck using Internet Explorer. You can try other browsers/OS's, but if you get errors, use IE instead.) You will be working through each of these simulations in lab this week here.
JK Flip-Flop Simulation.
Arithmetic Operations:
Half-Adder/Full-Adder.
4-bit Binary Adder/Subtractor using 2's Complement Arithmetic Observe how the Cout bit is the same as the sign-bit for 2's complement arithmetic. Does this circuit have any way of detecting an Overflow or Undeflow condition.
Ripple-Carry Adder.
BCD Adder.
Integer Multiplier.
Counters:
Asynchronous Counter. Check out both the UP and DOWN counter, and note the asynchronous CLEAR inputs on each FF. These can be use to put the Counter into a preferred state BEFORE the count begins.
Synchronous UP/DOWN Counter. Notice this counter is synchronous (all FFs are clocked by the same signal), can count UP or DOWN, has an ENABLE and has an ASYNCHRONOUS CLEAR input.
7490, 7492, 7493 Common TTL Counter chips, three different circuits/applications.
Digital Clock #1 and Digital Clock #2.
Programmable Logic Devices:
PLAs from Wikipedia
A simple presentation of PLA and PLD construction and operation: http://www.cs.umd.edu/class/sum2003/cms ... b/pla.html
Here is a tutorial and simulator for Programmable Logic Devices: http://tams-www.informatik.uni-hamburg. ... apter.html.
We will use this one on PLAs (Programmable Logic Arrays) as the basis for our discussion in class.
Week #7: (10/15-19) Higher Level Digital Functions
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